DIGITAL ELECTRONIC SYSTEMS

Prerequisites

The student must know: the fundamentals of information representation and transcoding between different representations, the fundamentals of algebra and Boolean algebra.

Contents

Topics of the course include:
Introduction to the digital system: Digital systems, Combinational and Sequential logic, Finite State Machine (FSM) and its models (Mealy and Moore), synchronous and asynchronous system, on real implementation of digital system (SSI and MSI circuits; PLD and FPGA systems – microprocessor systems).
Combinational systems: boolean algebra, switches functions and gates, truth tables and combinational design, implicants and implicates, sum of product form or product of sum form, map and methods for minimizing boolean functions (Karnaugh maps, maps with entered variable, Quine -McCluskey algorithm), hazard strong design. MSI block: encoders, decoders, multiplexers, demultiplexers, comparators. Binary numbering systems and codes. Binary, octal and hexadecimal numbering systems. Codes. Negative numbers in sign and module, 1’s complement, 2’s complement. Application to binary arithmetic.
Sequential systems: Flip-Flop function, Flip-Flop types: FF SR, FF SRE, FF JK, FF Master-Slave, FF edge triggered, FF T, FF D. Simple sequential systems: asynchronous counters; Synchronous sequencer, Register function and shift registers, PIPO, PISO, SIPO and SISO hardware core; set of register; Analysis of sequential networks. Timing diagrams.
Finite state machine and its description: state-transition diagram, PS/NS table; Algorithmic State Machine flowchart (ASM) and its application to counters, sequencer and register control.
Arithmetic hardware: Adders, half and Full Adder, ripple Adder, CLA, Carry skip adder, Subtractor, ALU; Multipliers: algorithm (sum loop), serial and parallel; Wallace multiplier, Booth’s algorithm
Register Transfer Model: Examples of analysis, design and synthesis of Control Units (based to FSM with ASM description) for Arithmetic block and “smart” register hardware.
Introduction to programmable logic (HW + SW)
Algorithmic approach to block HW design; from set of Moore machine to microprocessor architecture; selectable and programmable systems; VN architecture, Harvard architecture, ad hoc architectures. Outline of the architecture of microprocessors, microcontrollers, Digital Signal Processor (DSPor), Single Board Computer (SBC), Steps and tools for the development of a Programmed Logic design, HW and SW integration.

Assessment methods

The exam will consist in a written test related to an electronic digital project as developed in the course (20/30) and in an oral discussion on at least two topics from the course (13/30).
Alternatively, 2 partial written exams during the course reserved to students that are following the course, completed by a final oral discussion.